PCI-WDG-CSM

Details

This multifunction card contains a watchdog timer. Additionally, one or more options may be included on your card. These are: a computer power supply monitor, a computer internal temperature monitor, an optional capability to read the temperature, a fan-speed monitor, and an on-card buzzer to signal watchdog timeout. PCI-WDG-CSM continuously monitors critical PC functions. When a fault occurs, the card automatically generates outputs that can be used either to initiate corrective action or to generate alarms.

WATCHDOG

It’s a fact of life that computers and programs can fail. If a computer or program fails it can cause catastrophic damage. Even if a program merely locks up, an unattended computer could be down for days. There are two methods to reduce risk of computer or software failure; (a) redundancy and (b) a watchdog circuit. Neither method offers 100% assurance, but both of these methods reduce risk or consequences of failure. Redundancy, a duplication of computer circuitry, is very expensive. On the other hand, ACCES’ Watchdog card offers excellent protection from temporary malfunctions at very low cost.

Your application program must communicate with the watchdog circuit at prescribed intervals. If this communication (“prompt”) is missed, the Watchdog can be programmed to initiate a computer reset (reboot). If the reboot is successful, operation, may be returned to the previous application program. If the failure was temporary, proper operation is resumed. If, however, the failure is persistent, the Watchdog will continuously reset the computer. The more frequently the Watchdog is prompted (and shorter Watchdog time selected), the less time a faulty computer has to cause damage.

The method used by the WDG-CSM card to detect loss of computer function is as follows:

1. A type 82C54 counter/timer is used. This chip contains three 16-bit counters. A number greater than zero is set into the chip’s Counters 0 and 1 by your application program. The Watchdog is armed by software command and both counters begin counting down. As long as the computer is operating properly, both counters will be periodically reloaded to their original programmed values by your application program before both counters have counted down to zero.
2. If your software fails to reload the counters, then both counters continue counting until zero is reached (timeout). When the counters 0 and 1 reach zero, either the power-good line is held low for approximately 16 milliseconds (performing a hardware reset) through a relay contact, or external lines (either relay contacts or a de-bounced opto-isolated switch) are active while a buzzer sounds (if enabled). When a reset condition occurs, the reset circuit is active until a reset pulse returns from the system bus or power is cycled to the system.

The clock frequency to Counter 0 is derived from the computer’s color clock and is 2.0833 MHz. (The period is 1.117 µsec.) The output of Counter 0 is used as a clock to Counter 1. Since each counter can divide by any whole number from 2 to 65,536 (216), the watchdog timeout period may vary from about 10 microseconds to 4800 seconds.

The Watchdog card can generate an interrupt request one Counter 0 period-width before the reset timeout. For example, if a reset period of 60 seconds is used with a 5 milli-second delay stored in Counter 0 (the result of a maximum value delay), an interrupt would occur at 59.995 seconds. This gives the Interrupt handler software 5 milliseconds to refresh the watchdog before a reset action occurs. This should allow your software to take corrective actions if the system software continued to run but the software that should have reset the watchdog had failed. Also, this timeout-imminent warning can also be used to initiate an orderly shutdown of Windows programs.

The interrupt request (IRQ) output is tri-stated at a high-impedance when it is not sending an interrupt request (1 µsec). Thus, that IRQ number can be shared with other I/O cards that have shareable ability. IRQ’s 2 through 7, 10, 11, 12, 14, and 15 are available.

There are several outputs from the watchdog circuit:

1. Double-pole double-throw, Form C, relay contacts on the rear panel I/O connector
2. An opto-isolated reset output on the rear panel I/O connector
3. An opto-isolated complement of the reset output on the rear panel I/O connector
4. A buffered TTL CTRGATE (counter enabled) output on the rear panel I/O connector
5. TTL reset signal on internal terminal block TB1
6. The complement of that output at terminal 3 of TB1
7. A Watchdog 56KHz heartbeat on the rear panel I/O connector
8. Un-fused 5V DC output

As noted in items b. and c. above, opto-coupler outputs (one ON when the other is OFF) are provided for use where relay contact bounce could be a problem. Further, as noted in e. above, a buffered discrete output is also provided. This output goes high to signal a watchdog reset condition.

Finally, a 56 KHz, TTL-level, 50% duty cycle signal is provided at I/O connector pin 13 when the watchdog circuit is enabled and no reset is in progress. Otherwise, this output is in a low state.